Circuit Speed - up by Event Elimination

In this paper, we propose a novel technique for post-layout delay optimization. This technique identi es the Boolean space corresponding to late arriving transitions at the outputs of delay-critical subcircuits within the given circuit. There transitions are eliminated from the outputs by implementing the corresponding logic separately and merging them with the original circuit through some control logic. Experimental results suggest that this technique can speed up circuits even when the circuits have already been optimized for delay to the fullest extent.